`timescale 1ns/100ps

module MCYC_DIV_TB();
    reg rst,clk,start;
    reg unsigned[63:0]diver,divee;
    wire unsigned[63:0]div,mod;
    wire finish;
    wire unsigned[63:0]div_cmp,mod_cmp;
    always #5 clk=~clk;
	reg wip;
	initial begin
	   $dumpfile("MCYC_DIV_TB.vcd");
	   $dumpvars();
	   #0 rst=1;clk=0;wip=0;start=0;diver=0;divee=0;
	   #20 rst=0;
	   #60000 $finish;
	end
	assign div_cmp=divee/diver;
	assign mod_cmp=divee%diver;
	always@(posedge clk)
	begin
	  	if(!wip & finish & !start)
		begin
		  	diver<=$random+1;
			divee<=$random+1;
			start<=1;
		end
		else if(!finish)
		begin
		  	start<=0;
		end
		else if(wip & finish & !start);
		begin
			wip<=0;
		  	if(div_cmp==div)
			  	$display("DIVIDE OKAY!\n");
			else 
				$display("DIVIDE FAIL!\n");
			if(mod_cmp==mod)
				$display("REMAIN OKAY!\n");
			else 
				$display("REMAIN FAIL!\n");
		end
	end
    MulCyc_Div
	#(  .DIV_WIDTH(64),
	    .UNROLL_COEFF(0))
	DUT (
	.clk(clk),
	.rst(rst),
	.flush(1'b0),
	.DIVIDEND(divee),//被除数
	.DIVISOR(diver),//除数
	.start(start),
	.DIV(div),//商
	.MOD(mod),//余数
	.calc_done(finish) //Calculate done
	);
endmodule

